1. Field of the Invention
The present invention relates to an amplifier circuit used in audio systems.
2. Discussion of the Related Art
FIG. 1 shows a conventional audio amplifier circuit comprising an operational amplifier 10. The inverting input (−) of amplifier 10 is connected to an input terminal E of the system by a resistor 11 and a coupling capacitor 12 assembled in series. Output S of amplifier 10 is connected to its inverting input (−) by a resistor 13. Output S is also connected to a terminal of a capacitor 14 having another terminal forming output OUT of the amplifier circuit. Output OUT is connected to one of the two terminals of a load Q, typically a loudspeaker capable of emitting sounds according to the voltage applied thereacross, having its other terminal connected to a low reference supply or ground GND of the circuit. Capacitor 14 has the function of decoupling output signal VL from the D.C. offset voltage created by amplifier 10. The wanted output signal present on terminal VOUT thus is a dynamic signal, applied on terminal E. The non-inverting input (+) of amplifier 10 is connected to midpoint BP of a resistive dividing bridge comprised of two resistors 15 and 16 connected in series between a high supply terminal VCC and ground GND. A controllable switch 17, generally an MOS transistor, is interposed between high supply VCC and resistor 15. A signal SB for setting to standby controls switch 17 and the power supply of amplifier 10. Upon setting to standby, signal SB causes the setting to a high impedance state of output S, the turning-off of switch 17, and the stopping of the current sources of amplifier 10, which results in a significant reduction in power consumption. A capacitor 18 is connected between node BP and ground GND, in parallel with resistor 16. Capacitor 18 has the function of filtering the noise generated by resistors 15 and 16 and of absorbing possible voltage variations at supply terminal VCC.
The divider formed of resistors 15 and 16 sets the voltage at node BP, and thus the charge level of capacitor 18, to a reference voltage which sets a bias voltage of the audio amplifier. For example, the reference voltage may be chosen to be equal to half of supply voltage VCC, and the values of resistors 15, 16 are then set to the same value. In normal operation, in the absence of a signal at input terminal E, the charges of capacitors 12, 14, and 18 are maximum. Voltages VM of node M and VBP of node BP are equal to the reference voltage, the voltage across load Q being then zero. When a voltage is applied to input terminal E, voltage VIN is equal to the reference voltage, to which is added the variable component of the input voltage, coupling capacitor 12 suppressing the D.C. component of the input voltage.
Voltage VOUT across load Q is equal to the variable component of the input voltage multiplied by the amplification gain R13/R11. By choosing an appropriate ratio of the values of resistors 11 and 13, the peak-to-peak voltage of load Q can be amplified.
FIGS. 2A to 2E are partial simplified timing diagrams illustrating the variation of voltages along time at certain points of the amplifier circuit of FIG. 1 upon and at the end of a setting to standby. FIG. 2A illustrates signal SB for setting to standby. FIG. 2B illustrates voltage VBP, that is, the charge variation of decoupling capacitor 18. FIG. 2C illustrates voltage VS at output S of amplifier 10, that is, the charge variation of capacitor 14. FIG. 2D illustrates voltage VM, that is, the charge variation of coupling capacitor 12. FIG. 2E illustrates voltage VOUT across load Q. A time when the circuit of FIG. 1 is on is considered as the time origin (t=0) and FIGS. 2B to 2E illustrate the variation of the signals upon setting to standby of the circuit at a time t1 and upon restarting at a subsequent time t2 from this standby state.
For clarity, a test situation in which no input signal is applied on terminal E connected to ground GND is considered hereafter. Then, between times t=0 and t=1 of setting to standby, the voltages at nodes M, BP and S are stable, equal to reference voltage Vref.
At time t1, signal SB switches state and takes a state adapted to controlling the turning-off of switch 17 and of interrupting the supply of amplifier 10, for example, switching from a low state to a high state. Such a state of signal SB, and thus, the stand-by, is maintained until a subsequent time t2. At time t2, signal SB returns to its initial state, for example, low, enabling the supply of amplifier 10 and the turning-on of switch 17.
During the standby, load Q is inhibited. Capacitor 18 discharges through resistor 16. Coupling and decoupling capacitors 12 and 14 do not significantly discharge, only by a leakage current through the load. For clarity, it is considered, as illustrated in FIGS. 2C and 2D, that capacitors 12 and 14 remain charged during standby.
At time t2, amplifier 10 is “awake”, which causes an intermediary phase of discharge of capacitors 12 and 14. The discharge of capacitor 14, directly connected to load Q, is instantaneous and very fast. The discharge of capacitor 12 is delayed by resistors 11 and 13. The state switching of signal SB at time t2 also turns on switch 17. Decoupling capacitor 18 then charges through resistive divider 15, 16 to reference level Vref. This charge is transmitted to input and output capacitors 12 and 14 by copying of the voltage of node BP on node M. The intermediary discharge phase then ends at a time t3 after which capacitors 12 and 14 charge, as illustrated in FIGS. 2C and 2D, to reach the reference voltage. Capacitor 14, being charged by an amplified voltage, reaches the reference level at a time t4 prior to a time t5 at which coupling and decoupling capacitors 12 and 18 reach the reference level.
As illustrated in FIG. 2E, between times t2 and t5, voltage VOUT across load Q drops abruptly, then rapidly rises, crosses zero at time t3 and becomes positive before dropping back and stabilizing at a zero level at time t5. The positive peak appearing between times t3 and t4 translates as the transmission by loudspeaker Q of undesirable noise, unpleasant for the ear (pop noise).
To overcome this problem, various solutions have been provided. In particular, various modifications aiming at slowing down the discharge of decoupling capacitor 18 have been provided. However, such solutions also slow down its charge upon subsequent starting, which causes a relatively long latency time—that is, the duration separating time t5 of circuit stability from standby end time t2.